#---------  ------------#

#1.exit modelsim simulation
quit -sim

#2.clear messages
.main clear

#3.delete the existing work dir
if [file exists work] {vdel -all}

#--------- create library and mapping ------------#
#4.creat work dir
vlib work

#5.
vmap work work

#6.complie .v files
vlog -work work ./PC2FPGA_UART_TB.v
vlog -work work ./../rtl/precise_divider.v
vlog -work work ./../rtl/uart_receiver.v
vlog -work work ./../rtl/uart_transfer.v
# vlog -work work ./../rtl/PC2FPGA_UART_Test.v
# vlog -work work ./quartus_lib/220model.v
# vlog -work work ./quartus_lib/altera_mf.v
#vlog -work work ./../core/*.v

#7.start simulation
vsim -voptargs=+acc work.PC2FPGA_UART_TB

#8.add waves
	#add -divider { name }
add wave -group tb 				-radix unsigned PC2FPGA_UART_TB/*
add wave -group precise_divider -radix unsigned PC2FPGA_UART_TB/u_precise_divider/*
add wave -group uart_receiver 	-radix unsigned PC2FPGA_UART_TB/u_uart_receiver/*
add wave -group uart_transfer 	-radix unsigned PC2FPGA_UART_TB/u_uart_transfer/*

#9.run
run 100us